Simple PLA
A Programmable Logic Array (PLA) can be explained by reference to FIG. 1. The programming is done by blowing the proper fuses in a fuse bank 3, thus disconnecting nodes N from the respective AND gates 6 and 9. The remaining fuses connect the inputs with the AND gates 6 and 9, forming the circuit.
For example, if fuses 12 are blown, the circuit becomes that shown in FIG. 2. This particular circuit implements the logic function A.multidot.B+A.multidot.B. (The symbol .multidot. means logical AND, while the symbol + means logical OR. The symbol means logical NOT, or complement.) Other logic functions can be implemented by blowing other combinations of fuses.
In general, with the architecture of FIG. 1, the resulting logic function is a sum (ie, a logical ORing) of product terms. OR gate 4 performs the ORing. The product terms are produced by the AND gates: A.multidot.B is one product, and A.multidot.B is the other product. The connections feeding the AND gates, and which result from blowing the fuses, are termed an "AND-array."
The architecture of FIG. 1 is readily expandable to form more complex logic circuits, which implement more complex logic functions, by repeating the circuit, as shown in FIG. 3.